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» Allocator implementations for network-on-chip routers
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SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
14 years 20 days ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
CCS
2010
ACM
13 years 7 months ago
CRAFT: a new secure congestion control architecture
Congestion control algorithms seek to optimally utilize network resources by allocating a certain rate for each user. However, malicious clients can disregard the congestion contr...
Dongho Kim, Jerry T. Chiang, Yih-Chun Hu, Adrian P...
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
14 years 1 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
14 years 1 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
LCN
2005
IEEE
14 years 21 days ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha