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FPL
2007
Springer
126views Hardware» more  FPL 2007»
15 years 11 months ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Martin Schoeberl
DAC
2005
ACM
16 years 5 months ago
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 10 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
ANTS
2004
Springer
74views Algorithms» more  ANTS 2004»
15 years 10 months ago
Rational Divisors in Rational Divisor Classes
We discuss the situation where a curve C, defined over a number field K, has a known K-rational divisor class of degree 1, and consider whether this class contains an actual K-ra...
Nils Bruin, E. Victor Flynn
WSC
2000
15 years 6 months ago
Model composability as a research investment: responses to the featured paper
Responses to the featured paper are provided by four authors who represent different elements of the simulation research community: industry, private research laboratory, and univ...
Paul C. Davis, Paul A. Fishwick, C. Michael Overst...