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» Alternative Test Methods Using IEEE 1149.4
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VLSID
2002
IEEE
152views VLSI» more  VLSID 2002»
14 years 8 months ago
Verification of an Industrial CC-NUMA Server
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 8 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
GECCO
2007
Springer
156views Optimization» more  GECCO 2007»
14 years 1 months ago
Hierarchical genetic programming based on test input subsets
Crucial to the more widespread use of evolutionary computation techniques is the ability to scale up to handle complex problems. In the field of genetic programming, a number of d...
David Jackson
ICC
1997
IEEE
327views Communications» more  ICC 1997»
13 years 12 months ago
A Method to Partially Suppress ISI and MAI for DS SS CDMA Wireless Networks
- We propose a method to partially suppress ISI and MAI for DS SS CDMA schemes in wireless LANs. The method can be regarded as an alternative approach to combat ISI and in particul...
Beata J. Wysocki, Tadeusz A. Wysocki
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
13 years 11 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik