We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wi...
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...