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» Alternative Test Methods Using IEEE 1149.4
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ATS
2005
IEEE
132views Hardware» more  ATS 2005»
14 years 1 months ago
Concurrent Test Generation
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
Vishwani D. Agrawal, Alok S. Doshi
DATE
2005
IEEE
172views Hardware» more  DATE 2005»
14 years 1 months ago
Evolutionary Optimization in Code-Based Test Compression
We provide a general formulation for the code-based test compression problem with fixed-length input blocks and propose a solution approach based on Evolutionary Algorithms. In c...
Ilia Polian, Alejandro Czutro, Bernd Becker
ICTAI
2002
IEEE
14 years 21 days ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
ISMVL
2005
IEEE
90views Hardware» more  ISMVL 2005»
14 years 1 months ago
Test Generation and Fault Localization for Quantum Circuits
It is believed that quantum computing will begin to have a practical impact in industry around year 2010. We propose an approach to test generation and fault localization for a wi...
Marek A. Perkowski, Jacob Biamonte, Martin Lukac
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 20 days ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng