9 search results - page 2 / 2 » An ACL2 Proof of Write Invalidate Cache Coherence |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
PODC
2009
ACM
14 years 8 months ago
2009
ACM
d Abstract] Danny Hendler Department of Computer-Science Ben-Gurion University hendlerd@cs.bgu.ac.il Philipp Woelfel Department of Computer-Science University of Calgary woelfel@cp...