142 search results - page 2 / 29 » An Algorithm for Locating Logic Design Errors |
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
ICWMC
2006
IEEE
14 years 1 months ago
2006
IEEE
Geographic routing in wireless sensor networks is based on the prerequisite that every node has information about its current position, for instance via GPS or some localization a...
ICLP
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. This paper proposes a diagnosis algorithm for locating a certain kind of errors in logic programs: variable binding errors that result act symptoms during compile-time ch...
CISS
2008
IEEE
14 years 1 months ago
2008
IEEE
—The error floor of bit-interleaved coded modulation with iterative decoding (BICM-ID) can be minimized for a particular constellation by maximizing the harmonic mean of the squ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error dete...