Approximate logic circuits for low overhead, non-intrusive concurrent error detection

This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Mihir R. Choudhury, Kartik Mohanram
• Keywords: Approximate Logic Circuits, Concurrent Error Detection, DATE 2008, Hardware, Logic Circuits Scales