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» An Analog Leaf Cell for Analog Circuit Design
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ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 5 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
ISCAS
2003
IEEE
62views Hardware» more  ISCAS 2003»
14 years 18 days ago
Simple noise formulas for MOS analog design
The designer needs simple and accurate models to estimate noise in MOS transistors as a function of their size, bias point and technology. In this work, we present a simple, conti...
Alfredo Arnaud, Carlos Galup-Montoro
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Placement with symmetry constraints for analog layout design using TCG-S
In order to handle device matching for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis. In this paper, we deal with the module...
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hu...
DAC
2005
ACM
14 years 8 months ago
Scalable trajectory methods for on-demand analog macromodel extraction
Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations create...
Saurabh K. Tiwary, Rob A. Rutenbar
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
14 years 1 months ago
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters
– A new approach for diagnostic analysis of static errors in multi-step ADC based on the steepestdescent method is proposed. To set initial data, estimate the parameter update an...
Amir Zjajo, José Pineda de Gyvez