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FMCAD
1998
Springer
13 years 12 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
CORR
2007
Springer
128views Education» more  CORR 2007»
13 years 7 months ago
Verified Real Number Calculations: A Library for Interval Arithmetic
—Real number calculations on elementary functions are remarkably difficult to handle in mechanical proofs. In this paper, we show how these calculations can be performed within a...
Marc Daumas, David Lester, César Muñ...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
13 years 11 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
ETFA
2005
IEEE
14 years 1 months ago
Reuse of components in formal modeling and verification of distributed control systems
This paper describes formal modeling and verification of automation systems from the system engineering point of view. Reuse of model components is the key issue in order to bring...
Valeriy Vyatkin, Hans-Michael Hanisch
SAC
2008
ACM
13 years 7 months ago
A framework for performance evaluation and functional verification in stochastic process algebras
Despite its relatively short history, a wealth of formalisms exist for algebraic specification of stochastic systems. The goal of this paper is to give such formalisms a unifying ...
Hossein Hojjat, Mohammad Reza Mousavi, Marjan Sirj...