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HPCA
2008
IEEE
14 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
CORR
2006
Springer
103views Education» more  CORR 2006»
13 years 10 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford
ICASSP
2011
IEEE
13 years 1 months ago
Compressive sampling with a successive approximation ADC architecture
This paper proposes a compressive sampling scheme based on random temporal sampling using a successive approximation register (SAR) ADC architecture. Variable wordlength data samp...
Chenchi Luo, James H. McClellan
VTS
2007
IEEE
105views Hardware» more  VTS 2007»
14 years 4 months ago
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Attack resistance has been a critical concern for security-related applications. Various side-channel attacks can be launched to retrieve security information such as encryption k...
Chunsheng Liu, Yu Huang
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
14 years 1 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson