Sciweavers

2733 search results - page 77 / 547
» An Architecture for Compressive Imaging
Sort
View
DATE
2002
IEEE
104views Hardware» more  DATE 2002»
15 years 11 months ago
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
Luca Benini, Davide Bruni, Alberto Macii, Enrico M...
EUROMICRO
1999
IEEE
15 years 10 months ago
A Selective Compressed Memory System by On-Line Data Decompressing
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
15 years 10 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
ISCAPDCS
2003
15 years 7 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
ICIP
2004
IEEE
16 years 7 months ago
Multidimensional signal compression using multi-scale recurrent patterns with smooth side-match criterion
The recently proposed method for image compression based on multi-scale recurrent patterns, the MMP (Multidimensional Multiscale Parser) has been shown to perform well for a large...
Eddie B. L. Filho, Murilo B. de Carvalho, Eduardo ...