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INTEGRATION
2006
102views more  INTEGRATION 2006»
13 years 8 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
DSD
2010
IEEE
171views Hardware» more  DSD 2010»
13 years 7 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 9 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 1 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
CODES
2000
IEEE
14 years 29 days ago
Automatic test bench generation for simulation-based validation
In current design practice synthesis tools play a key role, letting designers to concentrate on the specificationof the system being designed by carrying out repetitive tasks such...
Marcello Lajolo, Luciano Lavagno, Maurizio Rebaude...