39 search results - page 7 / 8 » An Effective Bump Mapping Hardware Architecture Using Polar ... |
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
IOLTS
2005
IEEE
14 years 28 days ago
2005
IEEE
— In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in G...
CIKM
2001
Springer
13 years 12 months ago
2001
Springer
Our current concern is a scalable infrastructure for information retrieval (IR) with up-to-date retrieval results in the presence of frequent, continuous updates. Timely processin...
CODES
1999
IEEE
13 years 11 months ago
1999
IEEE
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
CF
2006
ACM
13 years 11 months ago
2006
ACM
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...