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» An Efficient Hardware Support for Control Data Validation
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ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 11 months ago
Efficient On-Chip Communications for Data-Flow IPs
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their ion in a system on chip. We abstract the communication behaviour of the data flow IP so a...
Antoine Fraboulet, Tanguy Risset
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
14 years 2 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 5 months ago
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
Michael Steffen, Joseph Zambreno
CASES
2010
ACM
13 years 5 months ago
Low cost multicast authentication via validity voting in time-triggered embedded control networks
Wired embedded networks must include multicast authentication to prevent masquerade attacks within the network. However, unique constraints for these networks make most existing m...
Christopher Szilagyi, Philip Koopman
ISCA
2008
IEEE
185views Hardware» more  ISCA 2008»
13 years 7 months ago
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware
Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely...
Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chu...