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ANCS
2009
ACM
13 years 6 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
CODES
2005
IEEE
14 years 2 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CONEXT
2009
ACM
13 years 9 months ago
RFDump: an architecture for monitoring the wireless ether
Networking researchers have been using tools like wireshark and tcpdump to sniff packets on physical links that use different types of datalink protocols, e.g. Ethernet or 802.11,...
Kaushik Lakshminarayanan, Samir Sapra, Srinivasan ...
WWW
2009
ACM
14 years 9 months ago
A trust management framework for service-oriented environments
Many reputation management systems have been developed under the assumption that each entity in the system will use a variant of the same scoring function. Much of the previous wo...
William Conner, Arun Iyengar, Thomas A. Mikalsen, ...
HPCC
2009
Springer
14 years 12 days ago
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory
Abstract--Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier. However, to be efficient, underlying TM system should protect only...
Sutirtha Sanyal, Sourav Roy, Adrián Cristal...