Sciweavers

26 search results - page 5 / 6
» An Efficient Indirect Branch Predictor
Sort
View
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 11 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
MICRO
2008
IEEE
107views Hardware» more  MICRO 2008»
14 years 2 months ago
A distributed processor state management architecture for large-window processors
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
Isidro Gonzalez, Marco Galluzzi, Alexander V. Veid...
CAL
2006
13 years 7 months ago
Performance modeling using Monte Carlo simulation
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
13 years 7 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
ANSS
2007
IEEE
13 years 11 months ago
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators
This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many in...
Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiro...