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VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 7 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
VLSID
2008
IEEE
83views VLSI» more  VLSID 2008»
14 years 7 months ago
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
We present a discrete-time time-domain vector fitting algorithm, called TD-VFz, for rational function macromodeling of port-to-port responses with discrete time-sampled data. The ...
Chi-Un Lei, Ngai Wong
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
14 years 1 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
14 years 7 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 21 days ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...