113 search results - page 18 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Skin effect makes interconnect resistance and inductance frequency dependent. This paper addresses the problem of efficiently estimating the signal characteristics of any RLC netw...