113 search results - page 8 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timi...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Acyclic partitioning on combinational boolean networks has wide range of applications, from multiple FPGA chip partitioning to parallel circuit simulation. In this paper, we prese...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
ICCAD
2003
IEEE
2003
IEEE
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
14 years 4 months ago
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...