34 search results - page 3 / 7 » An Evaluation of Directory Schemes for Cache Coherence |
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...