Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
Radharamanan Radhakrishnan, Lantz Moore, Philip A....
d Abstract) Luboˇs Brim and Jiˇr´ı Barnat Faculty of Informatics, Masaryk University, Brno, Czech Republic With the increase in the complexity of computer systems, it becomes e...
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
We provide a competitive analysis framework for online prefetching and buffer management algorithms in parallel I/O systems, using a read-once model of block references. This has ...
Rakesh D. Barve, Mahesh Kallahalla, Peter J. Varma...
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...