10213 search results - page 306 / 2043 » An Experimental Analysis of Parallel |
136
Voted
IPPS
1997
IEEE
15 years 7 months ago
1997
IEEE
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
132
Voted
SPIN
2007
Springer
15 years 9 months ago
2007
Springer
d Abstract) Luboˇs Brim and Jiˇr´ı Barnat Faculty of Informatics, Masaryk University, Brno, Czech Republic With the increase in the complexity of computer systems, it becomes e...
127
Voted
MICRO
2005
IEEE
15 years 9 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
146
Voted
IOPADS
1997
15 years 5 months ago
1997
We provide a competitive analysis framework for online prefetching and buffer management algorithms in parallel I/O systems, using a read-once model of block references. This has ...
141
Voted
VLSID
2001
IEEE
16 years 4 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...