Sciweavers

96 search results - page 13 / 20
» An Experimental Chip to Evaluate Test Techniques: Chip and E...
Sort
View
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
13 years 11 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
DIMEA
2008
190views Multimedia» more  DIMEA 2008»
13 years 9 months ago
Bridging the gap between the digital and the physical: design and evaluation of a mobile augmented reality guide for the museum
Can Augmented Reality (AR) techniques inform the design and implementation of a mobile multimedia guide for the museum setting? Drawing from our experience both on previous mobile...
Areti Damala, Pierre Cubaud, Anne Bationo, Pascal ...
ISPD
2004
ACM
189views Hardware» more  ISPD 2004»
14 years 23 days ago
Almost optimum placement legalization by minimum cost flow and dynamic programming
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
Ulrich Brenner, Anna Pauli, Jens Vygen
DAC
2003
ACM
14 years 8 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...
DFT
1997
IEEE
93views VLSI» more  DFT 1997»
13 years 11 months ago
An IDDQ Sensor for Concurrent Timing Error Detection
Abstract— Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system o...
Christopher G. Knight, Adit D. Singh, Victor P. Ne...