96 search results - page 3 / 20 » An Experimental Chip to Evaluate Test Techniques: Chip and E... |
ISQED
2005
IEEE
14 years 27 days ago
2005
IEEE
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
BMCBI
2010
2010
The IronChip evaluation package: a package of perl modules for robust analysis of custom microarrays
13 years 7 months ago
Background: Gene expression studies greatly contribute to our understanding of complex relationships in gene regulatory networks. However, the complexity of array design, producti...
SP
2010
IEEE
13 years 11 months ago
2010
IEEE
The computer systems security arms race between attackers and defenders has largely taken place in the domain of software systems, but as hardware complexity and design processes ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...