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FPL
2001
Springer
102views Hardware» more  FPL 2001»
14 years 10 days ago
Technology Trends and Adaptive Computing
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
Michael J. Flynn, Albert A. Liddicoat
DSD
2009
IEEE
141views Hardware» more  DSD 2009»
13 years 5 months ago
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
-- Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorith...
Ozgur Tasdizen, Ilker Hamzaoglu
ARC
2011
Springer
198views Hardware» more  ARC 2011»
12 years 11 months ago
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security
Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have alrea...
Sascha Mühlbach, Andreas Koch
CF
2007
ACM
13 years 12 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 2 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky