260 search results - page 8 / 52 » An FPGA Implemented Processor Architecture with Adaptive Res... |
ICES
2005
Springer
14 years 16 days ago
2005
Springer
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
IPPS
2003
IEEE
14 years 8 days ago
2003
IEEE
This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the tren...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
AHS
2007
IEEE
13 years 7 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...