1079 search results - page 23 / 216 » An Implementation of an Address Generator Using Hash Memorie... |
142
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ICESS
2007
Springer
15 years 9 months ago
2007
Springer
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
155
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ISCA
1995
IEEE
15 years 6 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
135
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NOCS
2010
IEEE
15 years 1 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
132
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MICRO
2003
IEEE
15 years 8 months ago
2003
IEEE
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
125
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ISVLSI
2005
IEEE
15 years 8 months ago
2005
IEEE
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...