1079 search results - page 34 / 216 » An Implementation of an Address Generator Using Hash Memorie... |
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
CN
2006
13 years 9 months ago
2006
Multidimensional packet classification has attracted considerable research interests in the past few years due to the increasing demand on policy based packet forwarding and secur...
FPL
2008
Springer
13 years 10 months ago
2008
Springer
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
PPOPP
2011
ACM
12 years 12 months ago
2011
ACM
The sparse grid discretization technique enables a compressed representation of higher-dimensional functions. In its original form, it relies heavily on recursion and complex data...