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DAC
2010
ACM
13 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
ECRTS
2007
IEEE
14 years 2 months ago
On Controllability and Feasibility of Utilization Control in Distributed Real-Time Systems
Feedback control techniques have recently been applied to a variety of real-time systems. However, a fundamental issue that was left out is guaranteeing system controllability and...
Xiaorui Wang, Yingming Chen, Chenyang Lu, Xenofon ...
SI3D
2005
ACM
14 years 1 months ago
Geopostors: a real-time geometry / impostor crowd rendering system
The simulation of large crowds of humans is important in many fields of computer graphics, including real-time applications such as games, as they can breathe life into otherwise...
Simon Dobbyn, John Hamill, Keith O'Conor, Carol O'...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
14 years 1 months ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
CODES
2000
IEEE
14 years 1 days ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf