81 search results - page 7 / 17 » An Integrated Framework for Architecture Level Exploration o... |
FDL
2003
IEEE
14 years 29 days ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
ERSA
2008
13 years 9 months ago
2008
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
EWSA
2005
Springer
14 years 1 months ago
2005
Springer
We propose a meta-framework called ‘Plastik’ which i) supports the specification and creation of runtime component-framework-based software systems and ii) facilitates and mana...