203 search results - page 10 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ISQED
2010
IEEE
14 years 2 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Abstract-- This paper presents a fundamental result on buffer sizing. Given an interconnection wire with n buffers evenly spaced along the wire, we would like to size all buffers s...
ISVLSI
2003
IEEE
14 years 20 days ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
LATIN
1998
Springer
13 years 11 months ago
1998
Springer
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...