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» An O(nlogn) time algorithm for optimal buffer insertion
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ICCD
2001
IEEE
154views Hardware» more  ICCD 2001»
14 years 4 months ago
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
COMPGEOM
2003
ACM
14 years 19 days ago
Updating and constructing constrained delaunay and constrained regular triangulations by flips
I discuss algorithms based on bistellar flips for inserting and deleting constraining (d − 1)-facets in d-dimensional constrained Delaunay triangulations (CDTs) and weighted CD...
Jonathan Richard Shewchuk
VLSISP
2002
112views more  VLSISP 2002»
13 years 7 months ago
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dat...
Ramaswamy Govindarajan, Guang R. Gao, Palash Desai
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
14 years 29 days ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
EMSOFT
2007
Springer
14 years 1 months ago
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
Software components are modular and can enable post-deployment update, but their high overhead in runtime and memory is prohibitive for many embedded systems. This paper proposes ...
Jiwon Hahn, Pai H. Chou