203 search results - page 7 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ISPD
2003
ACM
14 years 19 days ago
2003
ACM
— In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis syste...
ICCAD
2002
IEEE
14 years 10 days ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
A heuristic algorithm for a given topology of a multiple-source and multiple-sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting bu...
AINA
2007
IEEE
14 years 1 months ago
2007
IEEE
Embedded signal processing system is a typical type of application in embedded domain. Such systems typically have requirements on high real-time responsiveness and large buffer c...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...