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» An Optical Simulation of Shared Memory
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GLOBECOM
2007
IEEE
14 years 1 months ago
Bit Error Rate Performance of Multiple-Channel OTDM Demultiplexer Employing A Chained Symmetric Mach-Zehnder Switch
— This paper presents a high-speed multiple-channel optical time division multiplexed (OTDM) demultiplexer based on a chained symmetric Mach-Zehnder (CSMZ) switch. In CSMZ switch...
Hoa Le Minh, Zabih Ghassemlooy, Wai Pang Ng, Ming-...
INFOCOM
2008
IEEE
14 years 1 months ago
SRLG Failure Localization in All-Optical Networks Using Monitoring Cycles and Paths
—We introduce the concepts of monitoring paths (MPs) and monitoring cycles (MCs) for unique localization of shared risk linked group (SRLG) failures in all-optical networks. An S...
Satyajeet Ahuja, Srinivasan Ramasubramanian, Marwa...
PARCO
2003
13 years 8 months ago
Cache Memory Behavior of Advanced PDE Solvers
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
Dan Wallin, Henrik Johansson, Sverker Holmgren
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 15 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 7 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture