— This paper presents a high-speed multiple-channel optical time division multiplexed (OTDM) demultiplexer based on a chained symmetric Mach-Zehnder (CSMZ) switch. In CSMZ switch...
Hoa Le Minh, Zabih Ghassemlooy, Wai Pang Ng, Ming-...
—We introduce the concepts of monitoring paths (MPs) and monitoring cycles (MCs) for unique localization of shared risk linked group (SRLG) failures in all-optical networks. An S...
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer. The kernels implement...
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...