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CEC
2005
IEEE
14 years 2 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
ICANNGA
2009
Springer
163views Algorithms» more  ICANNGA 2009»
14 years 22 days ago
Elitistic Evolution: An Efficient Heuristic for Global Optimization
A new evolutionary algorithm, Elitistic Evolution (termed EEv), is proposed in this paper. EEv is an evolutionary method for numerical optimization with adaptive behavior. EEv uses...
Francisco Viveros Jiménez, Efrén Mez...
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 5 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
FORTE
2008
13 years 10 months ago
Detecting Communication Protocol Security Flaws by Formal Fuzz Testing and Machine Learning
Network-based fuzz testing has become an effective mechanism to ensure the security and reliability of communication protocol systems. However, fuzz testing is still conducted in a...
Guoqiang Shu, Yating Hsu, David Lee
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 9 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...