Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative sm...
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...