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» An analytic placer for mixed-size placement and timing-drive...
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FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
14 years 1 months ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
14 years 5 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
ISQED
2007
IEEE
107views Hardware» more  ISQED 2007»
14 years 2 months ago
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative sm...
Chen Li 0004, Cheng-Kok Koh
ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
14 years 2 months ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
DAC
2005
ACM
13 years 10 months ago
Faster and better global placement by a new transportation algorithm
We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the t...
Ulrich Brenner, Markus Struzyna