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DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 8 months ago
Power-aware Multimedia Systems using Run-time Prediction
The need for low-power multimedia processing is integral to portable and embedded devices such as cell phones, wireless terminals, multimedia handhelds and PDAs. The multimedia pr...
Pavan Kumar, Mani B. Srivastava
ICECCS
2009
IEEE
161views Hardware» more  ICECCS 2009»
14 years 2 months ago
Formal Modelling and Analysis of Business Information Applications with Fault Tolerant Middleware
Distributed information systems are critical to the functioning of many businesses; designing them to be dependable is a challenging but important task. We report our experience i...
Jeremy Bryans, John S. Fitzgerald, Alexander Roman...
ECBS
2008
IEEE
140views Hardware» more  ECBS 2008»
14 years 2 months ago
Towards Performance Related Decision Support for Model Driven Engineering of Enterprise SOA Applications
Model Driven Performance Engineering (MDPE) enables early performance feedback in a MDE process, in order to avoid late identification of performance problems which could cause si...
Mathias Fritzsche, Wasif Gilani, Ivor T. A. Spence...
IPPS
2007
IEEE
14 years 1 months ago
Predictive Resource Scheduling in Computational Grids
The integration of clusters of computers into computational grids has recently gained the attention of many computational scientists. While considerable progress has been made in ...
Clovis Chapman, Mirco Musolesi, Wolfgang Emmerich,...