55 search results - page 5 / 11 » An architectural exploration of via patterned gate arrays |
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...
GLVLSI
2003
IEEE
14 years 22 days ago
2003
IEEE
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...