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» An asynchronous fpga logic cell implementation
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FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 1 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
TVLSI
2008
119views more  TVLSI 2008»
13 years 7 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
13 years 7 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
13 years 11 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
14 years 27 days ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...