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» An automated design flow for 3D microarchitecture evaluation
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FPL
2006
Springer
223views Hardware» more  FPL 2006»
13 years 11 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
ISQED
2003
IEEE
119views Hardware» more  ISQED 2003»
14 years 1 months ago
System and Framework for QA of Process Design Kits
In this paper, we evaluate the dependencies between tools, data and environment in process design kits, and present a framework for systematically analyzing the quality of the des...
M. C. Scott, M. O. Peralta, Jo Dale Carothers
KBSE
1999
IEEE
13 years 12 months ago
Evolving Object-Oriented Designs with Refactorings
Refactorings are behavior-preserving program transformations that automate design evolution in object-oriented applications. Three kinds of design evolution are: schema transformat...
Lance Tokuda, Don S. Batory
DAC
2003
ACM
14 years 8 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
DAC
2005
ACM
14 years 8 months ago
Towards scalable flow and context sensitive pointer analysis
Pointer analysis, a classic problem in software program analysis, has emerged as an important problem to solve in design automation, at a time when complex designs, specified in t...
Jianwen Zhu