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BMCBI
2007
108views more  BMCBI 2007»
13 years 10 months ago
Publishing perishing? Towards tomorrow's information architecture
Scientific articles are tailored to present information in human-readable aliquots. Although the Internet has revolutionized the way our society thinks about information, the trad...
Michael R. Seringhaus, Mark B. Gerstein
JPDC
2007
167views more  JPDC 2007»
13 years 10 months ago
On the design of high-performance algorithms for aligning multiple protein sequences on mesh-based multiprocessor architectures
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
Diana H. P. Low, Bharadwaj Veeravalli, David A. Ba...
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
14 years 2 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 3 months ago
High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers
—This paper presents and compares three circuit architectures that are promising candidates to efficiently and dynamically supply GSM and EDGE RF power amplifiers in handsets. Th...
Yushan Li, Dragan Maksimovic
ITC
2003
IEEE
102views Hardware» more  ITC 2003»
14 years 3 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...