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» An efficient FIR filter architecture
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ISCAS
2002
IEEE
91views Hardware» more  ISCAS 2002»
14 years 8 days ago
Efficient digit-serial FIR filters with skew-tolerant domino
A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our ap...
Sungwook Kim, Gerald E. Sobelman
FPGA
1998
ACM
197views FPGA» more  FPGA 1998»
13 years 11 months ago
A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering
James R. Anderson, Siddharth Sheth, Kaushik Roy
SIGPRO
2008
105views more  SIGPRO 2008»
13 years 6 months ago
Peak constrained two-dimensional quadrantally symmetric eigenfilter design without transition band specification
Abstract-- The design of a two dimensional (2D) quadrantally symmetric FIR filter with peak constrained magnitude response is considered. We further considered the design specifica...
Chi-Wah Kok, Wan-Chi Siu, Ying-Man Law
SAMOS
2005
Springer
14 years 25 days ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...