112 search results - page 8 / 23 » An efficient FIR filter architecture |
AUTOMATICA
2007
13 years 7 months ago
2007
For fault-tolerant real-time filtering, an efficient two-filter architecture is proposed. In the two-filter architecture, a host filter is operated permanently. A compression filt...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
VLSID
1993
IEEE
13 years 11 months ago
1993
IEEE
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...