19 search results - page 4 / 4 » An efficient technique for device and interconnect optimizat... |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
TCAD
2002
13 years 7 months ago
2002
Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local character...
ISJGP
2010
13 years 4 months ago
2010
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...