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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 10 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
FPL
2003
Springer
128views Hardware» more  FPL 2003»
14 years 3 months ago
Case Study of a Functional Genomics Application
Although microarrays are already having a tremendous impact on biomedical science, they still present great computational challenges. We examine a particular problem involving the...
Tom Van Court, Martin C. Herbordt, Richard J. Bart...
ESCIENCE
2006
IEEE
14 years 1 months ago
Virtual Lab for fMRI: Bridging the Usability Gap
Grid technology can offer a powerful infrastructure for a broad spectrum of (scientific) application areas, but the uptake of grids by "real" applications has been slow....
Sílvia Delgado Olabarriaga, Piter T. de Boe...
IEEEINTERACT
2003
IEEE
14 years 3 months ago
The Effect of Compiler Optimizations on Pentium 4 Power Consumption
This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of ...
John S. Seng, Dean M. Tullsen
ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
14 years 2 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk