2488 search results - page 65 / 498 » An improvement in formal verification |
SNPD
2004
13 years 11 months ago
2004
A typical problem formal verification faces is the size of the model of a system being verified. Even for a small system, the state space of the model tends to grow exponentially (...
ISQED
2010
IEEE
13 years 12 months ago
2010
IEEE
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
ICSE
2009
IEEE-ACM
13 years 7 months ago
2009
IEEE-ACM
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
CSREAESA
2004
13 years 11 months ago
2004
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
ENTCS
2006
13 years 10 months ago
2006
Effective formal verification tools require that robust implementations of automatic procedures for first-order logic and satisfiability modulo theories be integrated into express...