73 search results - page 13 / 15 » An instruction-level energy model for embedded VLIW architec... |
TCAD
2002
13 years 7 months ago
2002
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
ISLPED
2003
ACM
14 years 24 days ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
DAC
2006
ACM
13 years 9 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
JEC
2006
13 years 7 months ago
2006
During the last two decades, Single Instruction Multiple Data (SIMD) processors have become important architectures in embedded systems for image processing applications. The main ...
DAC
2010
ACM
2010
ACM
A probabilistic and energy-efficient scheduling approach for online application in real-time systems
13 years 10 months ago
This work considers the problem of minimizing the power consumption for real-time scheduling on processors with discrete operating modes. We provide a model for determining the ex...