67 search results - page 4 / 14 » An integrated floorplanning with an efficient buffer plannin... |
ICCAD
1995
IEEE
14 years 3 days ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speciï...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
ICDE
1999
IEEE
14 years 10 months ago
1999
IEEE
In this paper we present an online method for managing a goaloriented buffer partitioning in the distributed memory of a network of workstations. Our algorithm implements a feedba...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...