5 search results - page 1 / 1 » An novel Methodology for Reducing SoC Test Data Volume on FP... |
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
DFT
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
DFT
2002
IEEE
14 years 3 months ago
2002
IEEE
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
VTS
2007
IEEE
14 years 5 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...