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» An on Chip ADC Test Structure
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ISQED
2003
IEEE
123views Hardware» more  ISQED 2003»
14 years 22 days ago
Advanced Module Packaging Method
An intermediate solution between conventional printed circuit board technology and wafer level packaging, WLP, is to fabricate interconnection circuits and flip chip assembly stru...
Peter C. Salmon
MR
2008
86views Robotics» more  MR 2008»
13 years 7 months ago
Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organ
The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies ...
J. S. Hwang, M. J. Yim, K. W. Paik
DSD
2006
IEEE
126views Hardware» more  DSD 2006»
14 years 1 months ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu...
ADC
2008
Springer
141views Database» more  ADC 2008»
14 years 1 months ago
Approximate Retrieval of XML Data with ApproXPath
Several XML query languages have been proposed that use XPath expressions to locate data. But XPath expressions might miss some data because of irregularities in the data and sche...
Lin Xu, Curtis E. Dyreson
ICCAD
2008
IEEE
98views Hardware» more  ICCAD 2008»
14 years 4 months ago
Statistical path selection for at-speed test
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...