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» An on Chip ADC Test Structure
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DATE
2008
IEEE
174views Hardware» more  DATE 2008»
14 years 1 months ago
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment
Due to high demand for hall sensors mostly in the automotive and industrial applications, development and manufacturing of hall sensors in System-on-Chip (SoC) became more importa...
Mustafa Badaroglu, Guy Decabooter, Francois Laulan...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 11 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
TODAES
2011
107views more  TODAES 2011»
13 years 2 months ago
Scan-based attacks on linear feedback shift register based stream ciphers
—In this paper, we present an attack on stream cipher implementations by determining the scan chain structure of the linear feedback shift registers in their implementations. Alt...
Yu Liu, Kaijie Wu, Ramesh Karri
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
- For sub-90nm technology nodes and below, random fluctuations of within-die physical process properties are also known as random on-chip variation (OCV). It impacts on the VLSI/So...
Jun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvi...
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...